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ltc4442/ltc4442-1 1 4442fb typical application features applications description high speed synchronous n-channel mosfet drivers the ltc ? 4442 is a high frequency gate driver designed to drive two n-channel mosfets in a synchronous buck dc/dc converter topology. the powerful driver capabil- ity reduces switching losses in mosfets with high gate capacitance. the ltc4442 features a separate supply for the input logic to match the signal swing of the controller ic. if the input signal is not being driven, the ltc4442 activates a shutdown mode that turns off both external mosfets. the input logic signal is internally level-shifted to the bootstrapped supply, which may function at up to 42v above ground. the ltc4442 contains undervoltage lockout circuits on both the driver and logic supplies that turn off the external mosfets when an undervoltage condition is present. the ltc4442 and ltc4442-1 have different undervoltage lockout thresholds to accommodate a wide variety of ap- plications. an adaptive shoot-through protection feature is also built-in to prevent power loss resulting from mosfet cross-conduction current. the ltc4442/ltc4442-1 are available in the thermally enhanced 8-lead msop package. synchronous buck converter driver wide v cc range: 6v to 9.5v 38v maximum input supply voltage adaptive shoot-through protection 2.4a peak pull-up current 5a peak pull-down current 8ns tg fall time driving 3000pf load 12ns tg rise time driving 3000pf load separate supply to match pwm controller drives dual n-channel mosfets undervoltage lockout thermally enhanced msop package distributed power architectures high density power modules ltc4442 driving 3000pf capacitive loads tg boost v in 32v gnd ts v logic v cc ltc4442 bg pwm v cc 6v in v out 4442 ta01a input (in) 5v/div bottom gate (bg) 5v/div top gate (tg-ts) 5v/div 10ns/div 4442 ta01b l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc4442/ltc4442-1 2 4442fb electrical characteristics absolute maximum ratings supply voltage v cc ......................................................... ?0.3v to 10v v logic .................................................... ?0.3v to 10v boost ? ts ........................................... ?0.3v to 10v in voltage .................................................. ?0.3v to 10v boost voltage .......................................... ?0.3v to 42v ts voltage ..................................................... ?5v to 38v ts + v cc ....................................................................42v driver output tg (with respect to ts) ....... ?0.3v to 10v driver output bg ........................................ ?0.3v to 10v operating temperature range (note 2).... ?40c to 85c junction temperature (note 3) ............................. 125c storage temperature range ................... ?65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) symbol parameter conditions min typ max units logic supply (v logic ) v logic operating range 3 9.5 v i vlogic dc supply current in = floating 730 850 a uvlo undervoltage lockout threshold v logic rising v logic falling hysteresis o o 2.5 2.4 2.75 2.65 100 3.0 2.9 v v mv gate driver supply (v cc ) v cc operating range 6 9.5 v i vcc dc supply current in = floating 300 380 a the o denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = v boost = 7v, v ts = gnd = 0v, v logic = 5v, unless otherwise noted. pin configuration 1 2 3 4 tg ts bg gnd 8 7 6 5 boost v cc v logic in top view ms8e package 8-lead plastic msop 9 gnd t ma 125c
ltc4442/ltc4442-1 3 4442fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc4442i/ltc4442i-1 are guaranteed to meet speci? cations from C40c to 85c. the ltc4442e/ltc4442e-1 are guaranteed to meet speci? cations from 0c to 85c with speci? cations over the C40c to 85c operating temperature range assured by design, characterization and correlation with statistical process controls. electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = v boost = 7v, v ts = gnd = 0v, v logic = 5v, unless otherwise noted. symbol parameter conditions min typ max units uvlo undervoltage lockout threshold v cc rising (ltc4442) v cc falling (ltc4442) hysteresis (ltc4442) 2.75 2.60 3.20 3.04 160 3.65 3.50 v v mv v cc rising (ltc4442-1) v cc falling (ltc4442-1) hysteresis (ltc4442-1) 5.6 4.7 6.2 5.3 850 6.7 5.8 v v mv bootstrapped supply (boost C ts) i boost dc supply current in = floating 325 400 a input signal (in) v ih(tg) tg turn-on input threshold v logic 5v, in rising v logic = 3.3v, in rising 3.0 1.9 3.5 2.2 4.0 2.6 v v v il(tg) tg turn-off input threshold v logic 5v, in falling v logic = 3.3v, in falling 3.25 2.09 v v v ih(bg) bg turn-on input threshold v logic 5v, in falling v logic = 3.3v, in falling 0.8 0.8 1.25 1.10 1.6 1.4 v v v il(bg) bg turn-off input threshold v logic 5v, in rising v logic = 3.3v, in rising 1.50 1.21 v v i in(sd) maximum current into or out of in in shutdown mode v logic 5v, in floating v logic = 3.3v, in floating 200 100 300 150 a a high side gate driver output (tg) v oh(tg) tg high output voltage i tg = C10ma, v oh(tg) = v boost C v tg 0.7 v v ol(tg) tg low output voltage i tg = 100ma, v ol(tg) = v tg C v ts 100 mv i pu(tg) tg peak pull-up current 1.5 2.4 a i pd(tg) tg peak pull-down current 1.5 2.4 a low side gate driver output (bg) v oh(bg) bg high output voltage i bg = C10ma, v oh(bg) = v cc C v bg 0.7 v v ol(bg) bg low output voltage i bg = 100ma 100 mv i pu(bg) bg peak pull-up current 1.4 2.4 a i pd(bg) bg peak pull-down current 3.5 5.0 a switching time t plh(tg) bg low to tg high propagation delay 20 ns t phl(tg) in low to tg low propagation delay 12 ns t plh(bg) tg low to bg high propagation delay 20 ns t phl(bg) in high to bg low propagation delay 12 ns t r(tg) tg output rise time 10% C 90%, c l = 3nf 12 ns t f(tg) tg output fall time 10% C 90%, c l = 3nf 8 ns t r(bg) bg output rise time 10% C 90%, c l = 3nf 12 ns t r(bg) bg output fall time 10% C 90%, c l = 3nf 5 ns t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (pd ? e ja c/w) note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
ltc4442/ltc4442-1 4 4442fb typical performance characteristics input thresholds vs v logic supply voltage input thresholds for v logic = 3.3v vs temperature bg or tg input threshold hysteresis vs v logic supply voltage quiescent supply current vs supply voltage quiescent supply current vs temperature v logic undervoltage lockout thresholds vs temperature v logic supply (v ) 34 0 input threshold (v) 2 5 5 7 8 4442 g01 1 4 3 6 9 10 v ih(tg) v il(tg) v il(bg) v ih(bg) temperature ( c) 0 input threshold (v) 1.0 2.0 3.0 0.5 1.5 2.5 ?0 20 50 80 4442 g02 110 ?0 v ih(tg) v logic = 3.3v v il(tg) v il(bg) v ih(bg) input thresholds for v logic 5v vs temperature temperature ( c) input threshold (v) 3 4 5 4442 g03 2 1 0 ?0 ?0 110 20 50 80 v ih(tg) v logic * 5v v il(tg) v il(bg) v ih(bg) v logic supply (v) 34 0 bg or tg input threshold hysteresis (v) 0.2 0.5 5 7 8 4442 g04 0.1 0.4 0.3 6 9 10 bg or tg input threshold hysteresis vs temperature temperature ( c) bg or tg input threshold hystersis (v) 0.25 0.30 0.35 4442 g05 0.15 0 ?0 ?0 20 50 80 110 0.40 0.20 0.10 0.05 v logic = 5v v logic = 3.3v supply voltage (v) 3 0 supply current (ma) 0.1 0.3 0.4 0.5 1.0 0.7 5 7 8 4442 g06 0.2 0.8 0.9 0.6 4 6 9 10 in floating i vlogic i boost i vcc temperature ( c) supply current (ma) 0.6 0.8 4442 g07 0.4 0.2 0.5 0.7 0.9 1.0 0.3 0.1 0 ?0 ?0 110 20 50 80 in floating v logic = 5v v cc = boost-ts = 7v i vlogic i boost i vcc temperature ( c) v logic uvlo threshold (v) 2.8 2.9 3.0 4442 g08 2.7 2.6 2.5 ?0 ?0 110 20 50 80 rising threshold falling threshold v cc undervoltage lockout thresholds vs temperature temperature ( c) v cc uvlo threshold (v) 5.0 6.0 7.0 4442 g09 4.0 3.0 4.5 5.5 6.5 3.5 2.5 2.0 ?0 ?0 110 20 50 80 ltc4442-1 rising threshold ltc4442 rising threshold ltc4442-1 falling threshold ltc4442 falling threshold
ltc4442/ltc4442-1 5 4442fb typical performance characteristics undervoltage lockout threshold hysteresis vs temperature switching supply current vs input frequency propagation delay vs v logic supply voltage output high voltage vs v cc supply voltage rise and fall time vs v cc supply voltage temperature ( c) uvlo threshold hysteresis (mv) 600 800 1000 4442 g10 400 200 500 700 900 300 100 0 ?0 ?0 110 20 50 80 ltc4442-1 v cc uvlo ltc4442 v cc uvlo v logic uvlo frequency (hz) 0 supply current (ma) 2 3 800k 4442 g11 1 0 200k 400k 600k 1m 4 i vcc i boost i vlogic no load v logic = 5v v cc = boost-ts = 7v switching supply current vs load capacitance load capacitance (nf) 0.1 0.3 3 0 supply current (ma) 1 10 100 11030 4442 g12 v logic = 5v v cc = boost-ts = 7v i cc or i boost f in = 500khz i cc or i boost f in = 100khz i logic f in = 500khz v logic supply voltage (v) 3 propagation delay (ns) 35 6 4442 g13 20 10 45 7 5 0 40 30 25 15 8910 no load v cc = boost-ts = 7v t plh(tg) t phl(tg) t plh(bg) t phl(bg) propagation delay vs v cc supply voltage v cc supply voltage (v) 4 35 30 25 20 15 10 5 0 79 4442 g14 56 810 propagation delay (ns) no load v logic = 5v boost-ts = v cc t plh(tg) t phl(tg) t plh(bg) t phl(bg) propagation delay vs temperature temperature ( c) propagation delay (ns) 25 30 35 4442 g15 15 0 ?0 ?0 20 50 80 110 40 20 10 5 no load v logic = 5v v cc = boost-ts = 7v t plh(tg) t phl(bg) t phl(tg) t plh(bg) v cc supply voltage (v) 4 0 bg or tg high output voltage (v) 2 4 6 5 6 78 4442 g16 9 8 10 1 3 5 7 9 10 boost-ts = v cc ?00ma ?ma ?0ma v cc supply voltage (v) 4 0 rise/fall time (ns) 5 10 15 20 567 t r(bg) 8 4442 g17 910 t r(tg) t f(tg) t f(bg) c load = 3.3nf boost-ts = v cc rise and fall time vs load capacitance load capacitance (nf) 13 1 rise/fall time (ns) 10 100 10 30 4442 g18 v cc = boost-ts = 7v t r(bg) t r(tg) t f(tg) t f(bg)
ltc4442/ltc4442-1 6 4442fb pin functions tg (pin 1): high side gate driver output (top gate). this pin swings between ts and boost. ts (pin 2): high side mosfet source connection (top source). bg (pin 3): low side gate driver output (bottom gate). this pin swings between v cc and gnd. gnd (pin 4, exposed pad pin 9): chip ground. the exposed pad must be soldered to the pcb ground for electrical contact and for rated thermal performance. in (pin 5): input signal. input referenced to an internal supply powered by v logic (pin 6) and referenced to gnd (pin 4). if this pin is ? oating, an internal resistive divider triggers a shutdown mode in which both bg (pin 3) and tg (pin 1) are pulled low. trace capacitance on this pin should be minimized to keep the shutdown time low. v logic (pin 6): logic supply. this pin powers the input buffer and logic. connect this pin to the power supply of the controller that is driving in (pin 5) to match input thresholds or to v cc (pin 7) to simplify pcb routing. v cc (pin 7): output driver supply. this pin powers the low side gate driver output directly and the high side gate driver output through an external diode connected between this pin and boost (pin 8). a low esr ceramic bypass capacitor should be tied between this pin and gnd (pin 4). boost (pin 8): high side bootstrapped supply. an ex- ternal capacitor should be tied between this pin and ts (pin 2). normally, a bootstrap diode is connected between v cc (pin 7) and this pin. voltage swing at this pin is from v cc C v d to v in + v cc C v d , where v d is the forward volt- age drop of the bootstrap diode.
ltc4442/ltc4442-1 7 4442fb block diagram 8 1 2 shoot- through protection three-state input buffer level shifter internal supply undervoltage lockout undervoltage lockout boost tg ts 3 6 bg 4442 bd v cc 7k 7k v logic 7 v cc 5 in 4 gnd 9 gnd timing diagram v il(bg) v il(tg) 90% in tg bg 90% 10% t r(tg) t plh(tg) 10% t r(bg) 4442 td t f(bg) t f(tg) t plh(bg) t phl(bg) t phl(tg)
ltc4442/ltc4442-1 8 4442fb operation overview the ltc4442 receives a ground-referenced, low voltage digital input signal to drive two n-channel power mosfets in a synchronous buck power supply con? guration. the gate of the low side mosfet is driven either to v cc or gnd, depending on the state of the input. similarly, the gate of the high side mosfet is driven to either boost or ts by a supply bootstrapped off of the switch node (ts). input stage the ltc4442 employs a unique three-state input stage with transition thresholds that are proportional to the v logic supply. the v logic supply can be tied to the controller ics power supply so that the input thresholds will match those of the controllers output signal. alternatively, v logic can be tied to v cc to simplify routing. an internal voltage regulator in the ltc4442 limits the input threshold values for v logic supply voltages greater than 5v. the relationship between the transition thresholds and the three input states of the ltc4442 is illustrated in figure 1. when the voltage on in is greater than the threshold v ih(tg) , tg is pulled up to boost, turning the high side mosfet on. this mosfet will stay on until in falls below v il(tg) . similarly, when in is less than v ih(bg) , bg is pulled up to v cc , turning the low side (synchronous) mosfet on. bg will stay high until in increases above the threshold v il(bg) . tg high tg high v ih(tg) v il(bg) v il(tg) v ih(bg) in tg low tg low bg low bg high 4442 f01 bg low bg high figure 1. three-state input operation the thresholds are positioned to allow for a region in which both bg and tg are low. an internal resistive divider will pull in into this region if the signal driving the in pin goes into a high impedance state. one application of this three-state input is to keep both of the power mosfets off while an undervoltage condition exists on the controller ic power supply. this can be ac- complished by driving the in pin with a logic buffer that has an enable pin. with the enable pin of the buffer tied to the power good pin of the controller ic, the logic buf- fer output will remain in a high impedance state until the controller con? rms that its supply is not in an undervoltage state. the three-state input of the ltc4442 will therefore pull in into the region where tg and bg are low until the controller has enough voltage to operate predictably. the hysteresis between the corresponding v ih and v il voltage levels eliminates false triggering due to noise during switch transitions; however, care should be taken to keep noise from coupling into the in pin, particularly in high frequency, high voltage applications. undervoltage lockout the ltc4442 contains undervoltage lockout detectors that monitor both the v cc and v logic supplies. when v cc falls below 3.04v or v logic falls below 2.65v, the output pins bg and tg are pulled to gnd and ts, respectively. this turns off both of the external mosfets. when v cc and v logic have adequate supply voltage for the ltc4442 to operate reliably, normal operation will resume. adaptive shoot-through protection internal adaptive shoot-through protection circuitry monitors the voltages on the external mosfets to ensure that they do not conduct simultaneously. the ltc4442 does not allow the bottom mosfet to turn on until the gate-source voltage on the top mosfet is suf? ciently low, and vice-versa. this feature improves ef? ciency by
ltc4442/ltc4442-1 9 4442fb operation 8 boost ltc4442 tg n1 q1 1 ts c gs c gd high side power mosfet v in up to 38v 2 7 v cc bg n2 q2 q3 3 gnd c gs 4442 f02 c gd low side power mosfet 4 load inductor figure 2. capacitance seen by bg and tg during switching eliminating cross-conduction current from ? owing from the v in supply through the mosfets to ground during a switch transition. output stage a simpli? ed version of the ltc4442s output stage is shown in figure 2. the pull-up device on both the bg and tg outputs is an npn bipolar junction transistor (q1 and q2). the bg and tg outputs are pulled up to within an npn v be (~0.7v) of their positive rails (v cc and boost, respectively). both bg and tg have n-channel mosfet pull- down devices (n1 and n2) which pull bg and tg down to their negative rails, gnd and ts. an additional npn bipolar junction transistor (q3) is present on bg to increase its pull-down drive current capacity. the large voltage swing of the bg and tg output pins is important in driving external power mosfets, whose r ds(on) is inversely proportional to its gate overdrive voltage (v gs C v th ). rise/fall time since the power mosfet generally accounts for the major- ity of power loss in a converter, it is important to quickly turn it on and off, thereby minimizing the transition time and power loss. the ltc4442s peak pull-up current of 2.4a for both bg and tg (q1 and q2) produces a rapid turn-on transition for the mosfets. this high current is capable of driving a 3nf load with a 12ns rise time. it is also important to turn the power mosfets off quickly to minimize power loss due to transition time; however, an additional bene? t of a strong pull-down on the driver outputs is the prevention of cross-conduction current. for example, when bg turns the low-side power mosfet off and tg turns the high-side power mosfet on, the volt- age on the ts pin will rise to v in very rapidly. this high frequency positive voltage transient will couple through the c gd capacitance of the low side power mosfet to the bg pin. if the bg pin is not held down suf? ciently, the voltage on the bg pin will rise above the threshold volt- age of the low side power mosfet, momentarily turning it back on. as a result, both the high side and low side mosfets will be conducting, which will cause signi? cant cross-conduction current to ? ow through the mosfets from v in to ground, thereby introducing substantial power loss. a similar effect occurs on tg due to the c gs and c gd capacitances of the high side mosfet. the ltc4442s powerful parallel combination of the n-channel mosfet (n2) and npn (q3) on the bg pull-down generates a phenomenal 5ns fall time on bg while driving a 3nf load. similarly, the 1 1 pull-down mosfet (n1) on tg results in a rapid 8ns fall time with a 3nf load. these powerful pull-down devices minimize the power loss as- sociated with mosfet turn-off time and cross-conduction current.
ltc4442/ltc4442-1 10 4442fb applications information power dissipation to ensure proper operation and long-term reliability, the ltc4442 must not operate beyond its maximum tem- perature rating. package junction temperature can be calculated by: t j = t a + (p d )( e ja ) where: t j = junction temperature t a = ambient temperature p d = power dissipation e ja = junction-to-ambient thermal resistance power dissipation consists of standby, switching and capacitive load power losses: p d = p dc + p ac + p qg where: p dc = quiescent power loss p ac = internal switching loss at input frequency f in p qg = loss due turning on and off the external mosfet with gate charge q g at frequency f in the ltc4442 consumes very little quiescent current. the dc power loss at v logic = 5v and v cc = v boost ? ts = 7v is only (730a)(5v) + (625a)(7v) = 8mw. at a particular switching frequency, the internal power loss increases due to both ac currents required to charge and discharge internal nodal capacitances and cross-conduc- tion currents in the internal logic gates. the sum of the quiescent current and internal switching current with no load are shown in the typical performance characteristics plot of switching supply current vs input frequency. the gate charge losses are primarily due to the large ac currents required to charge and discharge the capacitance of the external mosfets during switching. for identical pure capacitive loads c load on tg and bg at switching frequency ? n, the load losses would be: p cload = (c load )(f in )[(v boost C ts) 2 + (v cc ) 2 ] in a typical synchronous buck con? guration, v boost C ts is equal to v cc C v d , where v d is the forward voltage drop across the diode between v cc and boost. if this drop is small relative to v cc , the load losses can be approximated as: p cload 2(c load )(f in )(v cc ) 2 unlike a pure capacitive load, a power mosfets gate capacitance seen by the driver output varies with its v gs voltage level during switching. a mosfets capacitive load power dissipation can be calculated using its gate charge, q g . the q g value corresponding to the mosfets v gs value (v cc in this case) can be readily obtained from the manufacturers q g vs v gs curves. for identical mosfets on tg and bg: p qg 2(v cc )(q g )(f in ) to avoid damaging junction temperatures due to power dissipation, the ltc4442 includes a temperature monitor that will pull bg and tg low if the junction temperature exceeds 160c. normal operation will resume when the junction temperature cools to less than 135c. bypassing and grounding the ltc4442 requires proper bypassing on the v logic , v cc and v boost C ts supplies due to its high speed switching (nanoseconds) and large ac currents (amperes). careless component placement and pcb trace routing may cause excessive ringing and undershoot/overshoot.
ltc4442/ltc4442-1 11 4442fb to obtain the optimum performance from the ltc4442: a. mount the bypass capacitors as close as possible between the v logic and gnd pins, the v cc and gnd pins, and the boost and ts pins. the leads should be shortened as much as possible to reduce lead inductance. b. use a low inductance, low impedance ground plane to reduce any ground drop and stray capacitance. remember that the ltc4442 switches greater than 5a peak currents and any signi? cant ground drop will degrade signal integrity. applications information c. plan the power/ground routing carefully. know where the large load switching current is coming from and going to. maintain separate ground return paths for the input pin and the output power stage. d. keep the copper traces between the driver output pins and the load short and wide. e. be sure to solder the exposed pad on the back side of the ltc4442 packages to the board. correctly soldered to a 2500mm 2 double-sided 1oz copper board, the ltc4442 has a thermal resistance of approximately 40c/w. failure to make good thermal contact between the exposed back side and the copper board will result in thermal resistances far greater.
ltc4442/ltc4442-1 12 4442fb package description msop (ms8e) 0908 rev e 0.53 p 0.152 (.021 p .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 o C 6 o typ detail a detail a gauge plane 12 3 4 4.90 p 0.152 (.193 p .006) 8 8 1 bottom view of exposed pad option 7 6 5 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) 0.52 (.0205) ref 1.83 p 0.102 (.072 p .004) 2.06 p 0.102 (.081 p .004) 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 2.083 p 0.102 (.082 p .004) 2.794 p 0.102 (.110 p .004) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc 0.1016 p 0.0508 (.004 p .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref ms8e package 8-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1662 rev e)
ltc4442/ltc4442-1 13 4442fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 4/10 updated pin con? guration updated gnd (pin 4) in pin functions updated related parts 2 6 14 (revision history begins at rev b)
ltc4442/ltc4442-1 14 4442fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0410 rev b ? printed in usa related parts part number description comments ltc4449 high speed synchronous n-channel mosfet driver up to 38v supply voltage, 4.5v v cc 6.5v, 3.2a peak pull-up/ 4.5a peak pull-down ltc4444/ ltc4444-5 high voltage synchronous n-channel mosfet driver with shoot through protection up to 100v supply voltage, 4.5v/7.2v v cc 13.5v, 3a peak pull-up/ 0.55 peak pull-down ltc4446 high voltage synchronous n-channel mosfet driver without shoot through protection up to 100v supply voltage, 7.2v v cc 13.5v, 3a peak pull-up/ 0.55 peak pull-down ltc4440/ ltc4440-5 high speed, high voltage high side gate driver up to 80v supply voltage, 8v v cc 15v, 2.4a peak pull-up/ 1.5 peak pull-down ltc4441/ ltc4441-1 n-channel mosfet gate driver up to 25v supply voltage, 5v v cc 25v, 6a peak output current ltc1154 high side micropower mosfet driver up to 18v supply voltage, 85a quiescent current, h-grade available typical application tg boost d2 cmdsh3 c5 0.22 f m1 rjk0305 2 330 f 6 m2 rjk0301 2 v out 4442 ta02 l1 0.3 h r3 c6 gnd ts v logic v cc ltc4442-1 bg in c4 c3 r2 + + 1 f c2 c1 1k r sense r cm d1 r1 load rtn v 12sen sdata sclk smb_al_n pwrgd outen sync_in sync_out fault1 fault2 i out/ish i sh_gnd v cc pmbus interface v d33 v d25 7v v drive 12v 5v gnd ltc7510 pwm tempsen reset_n i senn i senp v senp v senn saddr v set fset v trim i maxset 1k 1k 1k 1k power management interface multiphase interface fault outputs i-share ltc7510/ltc4442-1 12v to 1.5v/30a digital step-down dc/dc converter with pmbus serial interface

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